1. Field of the Invention
The present invention relates to microprocessor systems, and more particularly, to a late cancel method and apparatus for a high performance microprocessor system with a backside cache memory.
2. Art Background
In order to avoid frequent, cycle consuming accesses of main memory, a microprocessor system frequently utilizes a cache memory. A cache memory is typically comprised of a relatively small amount of static random access memory (SRAM) which is both physically faster than main memory and arranged such that it can be addressed more rapidly than main memory. The microprocessor within the system then uses the faster cache memory to capture and store processor information (e.g. instructions or data) as they are used. Once this information is stored in the cache memory, the microprocessor is able to quickly and advantageously access it in cache memory rather than in main memory. The intelligent use of a cache memory can substantially enhance the performance of the overall microprocessor system.
Cache memories are organized and utilized in accordance with predetermined mapping policies, including for example, direct mapped, associative mapped, or set associative mapped policies. In the case of a direct mapped cache memory, for example, several blocks of main memory map directly to the same particular cache line in the cache memory. Of all the main memory blocks that map into a particular cache line in the cache memory, however, only one can actually reside in that cache line at one time.
When a microprocessor requests an instruction or data from a cache memory, the request can either result in a cache hit or a cache miss. A cache hit corresponds to the situation wherein the particular instruction or data requested by the microprocessor is presently stored in the cache memory. On the other hand, a cache miss corresponds to the situation wherein the particular instruction or data requested by the microprocessor is not presently stored in the cache memory. It will be appreciated that in the aforementioned direct mapped cache memory, a cache miss might correspond to a situation wherein the relevant cache line contains data or an instruction from a different memory block also mapped to this cache line. Under such circumstances, the data or instruction in the relevant cache line is "invalid" for purposes of the request, and a cache miss results. In the event of a cache miss, the microprocessor necessarily obtains the desired data or instruction from main memory.
In prior art systems, a microprocessor requesting an instruction from an external cache memory would first couple a request to the external cache memory for the desired instruction, wait until the external cache memory indicated a cache hit or miss, then, in the event of a cache hit, place the cache word provided by the external cache memory into the processor pipeline to be executed. In essence, the microprocessor would wait until the validity of the instruction was established (i.e. a cache hit) before processing the instruction. As will be described, the present invention provides for a microprocessor late cancel method and apparatus wherein a microprocessor requesting an instruction from cache memory does not wait until a cache hit or miss determination has been made before using the cache word provided by the cache memory. Instead, the cache word is placed in the processor pipeline immediately, before validity has been established. If the cache word is found to be invalid, it is canceled through a late cancel mechanism, prior to execution.